Cadence strikes new partnership with Samsung Foundry to deliver 2nm platform for AI chips
Cadence and Samsung Foundry announced a multi-year expansion of their collaboration to develop a full portfolio of Memory and Interface IP certified for Samsung Foundry’s second-generation 2nm process technology.
The signoff-ready platform integrates Cadence’s agentic AI digital, custom, 3D-IC, and system design and analysis flows to accelerate advanced silicon implementation for high-performance data centers, edge computing, and intelligent consumer devices. The certified EDA architecture houses a suite of advanced semiconductor design automation engines, combining the Innovus Implementation System for digital layout, Virtuoso Studio for custom analog mapping, and the Integrity 3D-IC Platform for vertical multi-die system planning.
Meanwhile, the verification framework relies on the Voltus IC Power Integrity solution to check structural power nets, alongside Quantus extraction, Tempus timing analysis, and the Pegasus Verification System to ensure foundry compliance before mask tapeout. The place-and-route optimization pipeline deploys the Genus Synthesis Solution to resolve circuit glitch power dissipation, using automated hierarchical structuring within Cadence Cerebrus Intelligent Chip Explorer to maximize total performance, power, and area metrics.
To address the physical constraints of advanced compute clusters, the platform establishes a comprehensive planning flow for hybrid copper bonding technology inside Samsung’s 3D Cube-H architecture, managing silicon interposer auto-routing directly beside the analysis block. The interface IP portfolio covers high-speed links spanning serial de-serializer lanes, PCIe, and UCIe connections, alongside custom integration of NVIDIA NVLink-C2C interconnect systems and CUDA-X GPU-accelerated simulation libraries.
All of these, combined with a specialized environment, allow chipmakers to offload high-density EDA workloads onto GPU accelerators, cutting down the compute runtime needed to verify complex advanced-node multi-die packaging layouts. The hardware node has also achieved active deployment through edge-computing developer Ambarella, which utilizes the certified PCIe 5.0 IP and system design kits to construct its next-generation 2nm edge AI SoC platform for autonomous machines, robotics, and multi-sensor edge perception applications.
